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UL
(R)
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
fCKO fCKi Vss SS/ SCK MISO MOSI
LS7366
(631) 271-0400 FAX (631) 271-0405
A3800
32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACE
GENERAL FEATURES: * Operating voltage: 3.0V to 5.5V (VDD - VSS) * 5V count frequency: 40MHz * 3V count frequency: 20MHz * 32-bit counter (CNTR). * 32-bit data register (DTR) and comparator. * 32-bit output register (OTR). * Two 8-bit mode registers (MDR0, MDR1) for programmable functional modes. * 8-bit instruction register (IR). * 8-bit status register (STR). * Latched Interrupt output on Carry or Borrow or Compare or Index. * Index driven counter load, output register load or counter reset. * Internal quadrature clock decoder and filter. * x1, x2 or x4 mode of quadrature counting. * Non-quadrature up/down counting. * Modulo-N, Non-recycle, Range-limit or Free-running modes of counting * 8-bit, 16-bit, 24-bit and 32-bit programmable configuration synchronous (SPI) serial interface * LS7366 (DIP); LS7366-S (SOIC); LS7366-TS (TSSOP) - See Figure 1SPI/MICROWIRE (Serial Peripheral Interface): * Standard 4-wire connection: MOSI, MISO, SS/ and SCK. * Slave mode only. GENERAL DESCRIPTION: LS7366 is a 32-bit CMOS counter, with direct interface for quadrature clocks from incremental encoders. It also interfaces with the index signals from incremental encoders to perform variety of marker functions. For communications with microprocessors or microcontrollers, it provides a 4-wire SPI/MICROWIRE bus.The four standard bus I/Os are SS/, SCK, MISO and MOSI. The data transfer between a microcontroller and a slave LS7366 is synchronous. The synchronization is done by the SCK clocks supplied by the microcontroller. Each transmission is organized in blocks of 1 to 5 bytes of data. A transmission cycle is intitiated by a high to low transition of the SS/ input. The first byte received in a transmission cycle is always an instruction byte, whereas the second through the fifth bytes are always interpreted as data bytes. A transmission cycle is terminated with the low to high transition of the SS/ input. Received bytes are shifted in at the MOSI input, MSB first, with the leading edges (high transition) of the SCK clocks. Output data are shifted out on the MISO output, MSB first, with the trailing edges (low transition) of the SCK clocks.
7366-012605-1
January 2005
PIN ASSIGNMENT TOP VIEW
14 13 12 LS7366 11 10 9 8 FIGURE 1 VDD CNT_EN A B INDEX DFLAG/ LFLAG/
1 2 3 4 5 6 7
Read and write commands cannot be combined. For example, when the device is shifting out read data on MISO output, it ignores the MOSI input, even though the SS/ input is active. SS/ must be terminated and reasserted before the device will accept a new command. The counter can be configured to operate as a 1, 2, 3 or 4-byte counter. When configured as a n-byte counter, the CNTR, DTR and OTR are all configured as n-byte registers, where n = 1, 2, 3 or 4. The content of the instruction/data identity is automatically adjusted to match the n-byte configuration. For example, if the counter is configured as a 2-byte counter, the instruction "write to DTR" expects 2 data bytes following the instruction byte. If the counter is configured as a 3-byte counter, the same instruction will expect 3 bytes of data following the instruction byte. Following the transfer of the appropriate number of bytes any further attempt of data transfer is ignored until a new instruction cycle is started by switching the SS/ input to high and then low. The counter can be programmed to operate in a number of different modes, with the operating characteristics being written into the two mode registers MDR0 and MDR1. Hardware I/Os are provided for event driven operations, such as processor interrupt and index related functions.
I/O Pins: Following is a description of all the input/output pins. A (Pin 12) B (Pin 11) Inputs. A and B quadrature clock outputs from incremental encoders are directly applied to the A and B inputs of the LS7366. These clocks are ideally 90 degrees out-of-phase signals. A and B inputs are validated by on-chip digital filters and then decoded for up/down direction and count clocks. In non-quadrature mode, A serves as the count input and B serves as the direction input (B = high enables up count, B = low enables down count). In non-quadrature mode, the A and B inputs are not filtered internally, and are instantaneous in nature. INDEX (Pin 10) Input. The INDEX is a programmable input that can be driven directly by the Index output of an incremental encoder. It can be programmed via the MDR to function as one of the following: LCNTR (load CNTR with data from DTR), RCNTR (reset CNTR), or LOTR (load OTR with data from CNTR). Alternatively, the INDEX input can be masked out for "no functionality". In quadrature mode, the INDEX input is validated with the filter clock in order to synchronize with the quadrature inputs A and B. To be valid, the INDEX signal in quadrature mode must overlap the condition in which both A and B are low or both A and B are high. In non-quadrature mode, however, the INDEX input is instantaneous in nature and totally independent of A and B. fCKi (Pin 2), fCK0 (Pin 1) Input, Output. A crystal connected between these 2 pins generates the basic clock for filtering the A, B and INDEX inputs in the quadrature count mode. Instead of a crystal the fCKi input may also be driven by an external clock. The frequency at the fCKi input is either divided by 2 (if MDR0 = 1) or divided by 1 (if MDR0 = 0) for the filter circuit. For proper filtering of the A, B and the Index inputs the following condition must be satisfied:
LFLAG/ (Pin 8), DFLAG/ (Pin 9) Outputs. LFLAG/ and DFLAG/ are programmable outputs to flag the occurences of Carry (counter overflow), Borrow (counter underflow), Compare (CNTR = DTR) and INDEX. The LFLAG/ is an open drain latched output. In contrast, the DFLAG/ is a pushpull instantaneous output. The LFLAG/ can be wired in multislave configuration, forming a single processor interrupt line. When active LFLAG/ switches to logic 0 and can be restored to the high impedence state only by clearing the status register, STR. In contrast, the DFLAG/ dynamically switches low with occurences of Carry, Borrow, Compare and INDEX conditions. The configuration of LFLAG/ and DFLAG/ are made through the control register MDR1. In free-running count mode LFLAG/ and DFLAG/ output the same status information in latched and dynamic form, respectively. In single-cycle mode the DFLAG/ outputs CY and BW signals independent of the MDR1 configuration. In range-limit and modulo-n modes, DFLAG/ outputs CMP signal in count-up direction (at CNTR = DTR) and BW signal when CNTR underflows independent of the MDR1 configuration. In effect, DFLAG/ generates mode-relevant marker signals in all modes, excepting the free-running count mode wherein MDR1 configures the output signal selection. MOSI (RXD) (Pin 7) Input. Serial output data from the host processor is shifted into the LS7366 at this input. MISO (TXD) (Pin 6) Output. Serial output data from the LS7366 is shifted out on the MISO (Master In Slave Out) pin. The MISO output goes into high impedance state when SS/ input is at logic high, providing multiple slave-unit serial outputs to be wire-ORed. SCK (Pin 5) Input. The SCK input serves as the shift clock input for transmitting data in and out of LS7366 on the MOSI and the MISO pins, respectively. Since the LS7366 can operate only in the slave mode, the SCK signal is provided by the host processor as a means for synchronizing the serial transmission between itself and the slave LS7366. REGISTERS: The following is a list of LS7366 internal registers: Upon power-up the registers DTR, CNTR, STR, MDR0 and MDR1 are reset to zero. DTR. The DTR is a software configurable 8, 16, 24 or 32-bit input data register which can be written into directly from MOSI, the serial input. The DTR data can be transferred into the 32-bit counter (CNTR) under program control or by hardware index signal. The DTR can be cleared to zero by software control. In certain count modes, such as modulo-n and range-limit, DTR holds the data for "n" and the count range, respectively. In compare operations, whereby compare flag is set, the DTR is compared with the CNTR.
ff 4fQA
Where ff is the internal filter clock frequency derived from the fCKi in accordance with the status of MDR0 and fQA is the maximum frequency of Clock A in quadrature mode. In non-quadrature count mode, fCKi is not used and should be tied off to any stable logic state. SS/ (Pin 4) A high to low transition at the SS/ (Slave Select) input selects the LS7366 for serial bi-directional data transfer; a low to high transition disables serial data transfer and brings the MISO output to high impedance state. This allows for the accommodation of multiple slave units on the serial I/O. CNT_EN (Pin 12) Input. Counting is enabled when CNT_EN input is high; counting is disabled when this input is low. There is an internal pull-up resistor on this input.
7366-012405-2
CNTR. The CNTR is a software configurable 8, 16, 24 or 32-bit up/down counter which counts the up/down pulses resulting from the quadrature clocks applied at the A and B inputs, or alternatively, in non-quadrature mode, pulses applied at the A input. By means of IR intructions the CNTR can be cleared, loaded from the DTR or in turn, can be transferred into the OTR. The "clear CNTR" and the "load CNTR" commands in the "range-limit" mode, however have limitations. In this mode when the CNTR is frozen in up count direction at CNTR = DTR, a "clear CNTR" command will only function if the count direction is reversed from up to down. Similarly, in the down direction at CNTR = 0, a "load CNTR" command will only function if the direction is reversed from down to up. OTR. The OTR is a software configuration 8, 16, 24 or 32-bit register which can be read back on the MISO output. Since instantaneous CNTR value is often needed to be read while the CNTR continues to count, the OTR serves as a convenient dump site for instantaneous CNTR data which can then be read without interfering with the counting process. STR. The STR is an 8-bit status register which stores count related status information. CY 7 BW 6 CMP 5 IDX 4 CEN 3 PLS 2 U/D 1 S 0 PLS: Power loss indicator latch; set upon power up U/D: Count direction indicator: 0: count down, 1: count up S: Sign bit. 1: negative, 2: positive A "CLR STR" command to IR resets all status bits except CEN and U/D. In quadrature mode, if the quadrature clocks have been halted, the status bits CY, BW and CMP are not affected by a "CLR STR" command under the following conditions: CY: If CNTR = FFFFFFFF with status bit U/D = 1 BW: If CNTR = 0 with status bit U/D = 0 CMP: If CNTR = DTR In non-quadrature mode the same rules apply if input A is held at logic low. B2 B1 B0 = XXX (Don't care) B5 B4 B3 = 000: Select none = 001: Select MDR0 = 010: Select MDR1 = 011: Select DTR = 100: Select CNTR = 101: Select OTR = 110: Select STR = 111: Select none B7 B6 = 00: CLR register = 01: RD register = 10: WR register = 11: LOAD register
CY: Carry (CNTR overflow) latch BW: Borrow (CNTR underflow) latch CMP: Compare (CNTR = DTR) latch IDX: Index latch CEN: Count enable status: 0: counting disabled, 1: counting enabled
IR. The IR is an 8-bit register that fetches instruction bytes from the received data stream and executes them to perform such functions as setting up the operating mode for the chip (load the MDR) and data transfer among the various registers. B7 B6 B5 B4 B3 B2 B1 B0
The actions of the four functions, CLR, RD, WR and LOAD are elaborated in Table 1. TABLE 1 Register MDR0 MRD1 DTR CNTR OTR STR MDR0 MDR1 DTR CNTR OTR STR MDR0 MDR1 DTR CNTR OTR STR MDR0 MDR1 DTR CNTR OTR
Number of Bytes OP Code
1
CLR
2 to 5
RD
2 to 5
WR
1
LOAD
Operation Clear MDR0 to zero Clear MDR1 to zero None Clear CNTR to zero None Clear STR to zero Output MDR0 serially on TXD (MISO) Output MDR1 serially on TXD (MISO) None Transfer CNTR to OTR, then output OTR serially on TXD (MISO) Output OTR serially on TXD (MISO) Output STR serially on TXD (MISO) Write serial data at RXD (MOSI) into MDR0 Write serial data at RXD (MOSI) into MDR1 Write serial data at RXD (MOSI) into DTR None None None None None None Transfer DTR to CNTR in "parallel" Transfer CNTR to OTR in "parallel"
7366-012405-3
MDR0. The MDR0 (Mode Register 0) is an 8-bit read/write register that sets up the operating mode for the LS7366. The MDR0 is written into by executing the "write-to-MDR0" instruction via the instruction register. Upon power up MDR0 is cleared to zero. The following is a breakdown of the MDR bits: B7 B6 B5 B4 B3 B2 B1 B0
B1 B0 = 00: non-quadrature count mode. (A = clock, B = direction). = 01: x1 quadrature count mode (one count per quadrature cycle). = 10: x2 quadrature count mode (two counts per quadrature cycle). = 11: x4 quadrature count mode (four counts per quadrature cycle). B3 B2 = 00: free-running count mode. = 01: single-cycle count mode (counter disabled with carry or borrow, re-enabled with reset or load). = 10: range-limit count mode (up and down count-ranges are limited between DTR and zero, respectively; counting freezes at these limits but resumes when direction reverses). = 11: modulo-n count mode (input count clock frequency is divided by a factor of (n+1), where n = DTR, in both up and down directions). B5 B4 = 00: disable index. = 01: configure index as the "load CNTR" input (transfers DTR to CNTR). = 10: configure index as the "reset CNTR" input (clears CNTR to 0). = 11: configure index as the "load OTR" input (transfers CNTR to OTR). B6 = 0: = 1: B7 = 0: = 1: Negative index input Positive index input Filter clock division factor = 1 Filter clock division factor = 2
MDR1. The MDR1 (Mode Register 1) is an 8-bit read/write register which is appended to MDR0 for additional modes. Upon power-up MDR1 is cleared to zero. B7 B1 B0 = 00: = 01: = 10: = 11: B2 = 0: = 1: B3 = : B4 = 0: = 1: B5 = 0: = 1: B6 = 0: = 1: B7 = 0: = 1: B6 B5 B4 B3 B2 B1 B0
4-byte counter mode 3-byte counter mode 2-byte counter mode. 1-byte counter mode Enable counting Disable counting not used NOP FLAG on IDX (B4 of STR) NOP FLAG on CMP (B5 of STR) NOP FLAG on BW (B6 of STR) NOP FLAG on CY (B7 of STR)
NOTE: Applicable to both LFLAG/ and DFLAG/
ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to Vss) Parameter DC Supply Voltage Voltage Operating Temperature Storage Temperature Symbol VDD VIN TA TSTG Values +7.0 Vss - 0.3 to VDD + 0.3 -25 to +85 -65 to +150 Unit V V oC oC
7366-112204-4
DC Electrical Characteristics. (TA = -25C to +85C) Parameter Supply Voltage Supply Current Input Voltages fCKi, Logic high fCKi, Logic Low All other inputs, Logic High Symbol VDD IDD IDD VCH VCH VCL VCL VAH VAH VAL VAL IIEL IIEL IIEH IIEH IOFL IOFL IOCL IOCL IOCH IOCH IOML IOML IOMH IOMH Min. 3.0 300 700 0.7 1.3 0.5 1.0 -1.3 -3.2 0 -1.3 -3.2 1.3 3.2 -1.5 -3.8 1.5 3.8 TYP 400 800 2.1 3.5 0.9 1.5 1.9 3.2 0.7 1.2 3.0 10.0 1.0 4.0 0 -2.0 -4.0 0 -2.0 -4.0 2.0 4.0 -2.4 -4.8 2.4 4.8 Max. 5.5 450 950 2.3 3.7 2.1 3.5 5.0 15.0 3.0 6.0 0 Unit V A A V V V V V V V V A A A A A mA mA mA mA mA mA mA mA mA mA mA Remarks VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VAL = 0.7V, VDD = 3.0V VAL = 1.2V, VDD = 5.0V VAH = 1.9V, VDD = 3.0V VAH = 3.2V, VDD = 5.0V VOUT = 0.5V, VDD = 3.0V VOUT = 0.5V, VDD = 5.0V Open Drain Output VOUT VOUT VOUT VOUT = 0.5V, VDD = 3.0V = 0.5V, VDD = 5.0V = 2.5V, VDD = 3.0V = 4.5V, VDD = 5.0V
All other inputs, Logic Low Input Currents: CNT_EN Low
CNT_EN High All other inputs, High or Low Output Currents: FLAG Sink FLAG Source fCKO Sink fCKO Source TXD/MISO: Sink
VOUT = 0.5V, VDD = 3.0V VOUT = 0.5V, VDD = 5.0V VOUT = 0.5V, VDD = 3.0V VOUT = 0.5V, VDD = 5.0V
Source
Transient Characteristics. (TA = -25C to +85C, VDD = 5V 10%) Parameter (See Fig. 2 & 3) SCK High Pulse Width SCK Low Pulse Width SS/ Set Up Time SS/ Hold Time Quadrature Mode (See Fig. 4, 6 & 7) fCKI High Pulse Width fCKI Pulse Width fCKI Frequency Effective Filter Clock fF Period Effective Filter Clock fF frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay x1 / x2 / x4 Count Clock Pulse Width Index Input Pulse Width Index Set Up Time Index Hold Time Quadrature clock to DFLAG/ or LFLAG/ delay DFLAG/ output width
7366-102204-5
Symbol tCH tCL tCSL tCSH
Min. Value 100 100 100 100
Max.Value -
Unit ns ns ns ns
Remarks -
t1 t2 fFCK t3 t3 fF t4 t5 fQA, fQB tQ1 tQ2 tid tis tih tfl tfw
12 12 25 50 26 52 4t3 12 32 4.5t3 26
40 40 9.6 5t3 5 5 5.5t3 -
ns ns MHz ns ns MHz ns ns MHz ns ns ns ns ns ns
t3 = t1+t2, MDR0 <7> = 0 t3 = 2(t1+t2), MDR0 <7> = 1 fF = 1/ t3 t4 > t3 t5 2t3 fQA = fQB < 1/4t3 tQ2 = (t3)/2 tid > t4 tfw = t4
Parameter Non-Quadrature Mode (See Fig. 5 & 8) Clock A - High Pulse Width Clock A - Low Pulse Width Direction Input B Set-up Time Direction Input B Hold Time Clock Frequency (non-Mod-N) Clock to DFLAG/ or LFLAG/ delay DFLAG/ output width
Symbol
Min. Value
Max.Value
Unit
Remarks
t6 t7 t8S t8H fA t9 t10
12 12 12 10 20 12
40 -
ns ns ns ns MHz ns ns
fA = (1/(t6 + t7)) t10 = t7
Transient Characteristics. (TA = -25C to +85C, VDD = 3.3V 10%) Parameter (See Fig. 2 & 3) SCK High Pulse Width SCK Low Pulse Width SS/ Set Up Time SS/ Hold Time Quadrature Mode (See Fig. 4, 6 & 7) fCKI High Pulse Width fCKI Pulse Width fCKI Frequency Effective Filter Clock fF Period Effective Filter Clock fF frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay x1/x2/x4 Count Clock Pulse Width Index Input Pulse Width Index Set Up Time Index Hold Time Quadrature clock to DFLAG/ or LFLAG/ delay DFLAG/ output width Symbol tCH tCL tCSL tCSH Min. Value 120 120 120 120 Max.Value Unit ns ns ns ns Remarks -
t1 t2 fFCK t3 t3 fF t4 t5 fQA, fQB tQ1 tQ2 tid tis tih tfl tfw
24 24 50 100 52 105 4t3 25 60 4.5t3 52
20 20 4.5 5t3 10 10 5.5t3 -
ns ns MHz ns ns MHz ns ns MHz ns ns ns ns ns ns
t3 = t1+t2, MDR0 <7> = 0 t3 = 2(t1+t2), MDR0 <7> = 1 fF = 1/t3 t4 > t3 t5 2t3 fQA = fQB < 1/4t3 tQ2 = (t3)/2 tid > t4 tfw = t4
Non-Quadrature Mode (See Fig. 5 & 8) Clock A - High Pulse Width Clock A - Low Pulse Width Direction Input B Set-up Time Direction Input B Hold Time Clock Frequency (non-Mod-N) Clock to DFLAG/or LFLAG/ delay DFLAG/ output width
t6 t7 t8S t8H fA t9 t10
24 24 24 24 40 24
40 -
ns ns ns ns MHz ns ns
fA = (1/(t6 + t7)) t10 = t7
7366-102204-6
tCSL
SS/
START OF NEW COMMAND
tCSH
tCH
SCK
MOSI BIT # 7 6 5 4 3 WR MDR1 X 2 X 1 X 0 DATA D7 D6 D5 D4 D3 D2 D1 D0 X 7 6 54 3 2 1 0 7 6 54 3 RD MDR1
tCL
X 2
X 1
X RANDOM DATA 0
MISO BIT #
D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0
TRI-STATE
NOTE: Write to MDR1 followed by Read from MDR1 operation
FIGURE 2. WR MDR1 - RD MDR1
tCSI
SS/
SCK
MOSI BIT #
RD
CNTR X X 1 X 0 BYTE 1 BYTE 0 RANDOM DATA
CLR
STR X X 1 X 0
7
6
5
4
3
2
7
6
5
4
3
2
MISO BIT #
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
TRI-STATE
NOTE: Read CNTR (in 2-byte configuration) followed by CLR STR operation.
FIGURE 3. RD CNTR - CLR STR
t1 f CKi f f (Note 4)
(MDR0 <7> = 0)
t2
t3 t3 t5 t4 t is
Note 1
f f (Note 4)
(MDR0 <7> = 1)
t5 t4 t ih t4 t is
Note 2
A
t4 t ih
B
INDEX
t id
Positive index coincident with both A and B high. Positive index coincident with both A and B low. The index logic level in the above examples are inverted for negative index. fF is the internal effective filter clock. FIGURE 4. fCKI, A, B and INDEX
Note 1. Note 2. Note 3. Note 4.
7366-112204-7
DOWN
UP
DOWN
t6
t7
t8s
t8H
FIGURE 5. COUNT (A) AND DIRECTION (B) INPUTS IN NON-QUADRATURE MODE
UP A B
X4_CLK
(see note)
DOWN
tQ1
X2_CLK
(see note)
tQ2
X1_CLK
(see note)
Note: x1, x2, and x4 CLKs are internal up/down clocks derived from filtered and decoded quadrature clocks. FIGURE 6. A/B QUADRATURE CLOCKS VS INTERNAL COUNT CLOCKS
UP A B
X4_CLK
DOWN
CNTR DFLG/
FFFFFC
FFFFFD
FFFFFE
FFFFFF
000000
000001
000002
000001 000000 FFFFFF
FFFFFE
FFFFFD
tfl CY tfl
LFLG/
(SHOWN WITH PR=000OO1)
CMP
BW tfw
Note: CNTR values are indicated in 3-byte mode
FIGURE 7. QUADRATURE CLOCKS VS FLAG OUTPUTS
7366-112204-8
UP B
DOWN
A
(Shown with PR=2)
CNTR LFLG/
FFFFFC
FFFFFD
FFFFFE
FFFFFF
000000
000002 000001
000000
t9
CY-LATCH
(clear STR)
BW-LATCH
CNTR DISABLED
INDEX
CNTR ENABLED (load CNTR)
t11
CNTR DISABLED
NOTE: CNTR values are indicated in 2-byte mode
FIGURE 8. SINGLE-CYCLE, NON-QUADRATURE
B A
UP
DOWN
(Shown with PR=3)
CNTR 000000 000001 000002 000003 000000 000001 000002 DFLAG/
000001 000000 000003 000002 000001
CMP
BW
NOTE: CNTR values are indicated in 1-byte mode
FIGURE 9. MODULO-N, NON-QUADRATURE
B A
UP
DOWN
(Shown with PR=3)
CNTR 000000 000001 000002 DFLAG/
000003
000002 000001
000000
CMP
CMP
CMP
CMP
BW
BW
BW
NOTE: CNTR values are indicated in 1-byte mode
FIGURE 10. RANGE-LIMIT, NON-QUADRATURE
7366-112204-9
(8) CLOCK CONTROL I0 DATA CONTROL RXD/MOSI 7
4 12
SCK
5
V+
I0 SHIFT REG (8)
(8)
BUFFER
6 TXD/MIS0
EN_DTR SPI_XMIT/ DTR (32) POR
SS/ A
B
11
FILTER MODE CONTROL
CNTR (32)
EN_CNTR
LOAD
CMPR
BUFFER 9 DFLAG/
INDEX 10
2 1
OTR (32) /2 V+ MDR0<7> MUX
EN_OTR
LOAD
8 LFLAG/
FLAG LOGIC
fCKi fCK0
EN_MDR0 MDR0 (8) FLAGS
CNT_EN 13 WR MDR1 (8) POR (V+) (V-) FLAGS FLAG MASK RD STR (8) EN_STR POR GEN CLR EN_DTR EN_CNTR EN_OTR IR POR EN_MDR1
VDD 14 Vss
3
(5) EN_MDR0
LOAD CLR RDWR
EN_MDR1 EN_STR
FIGURE 11. LS7366 BLOCK DIAGRAM
MISO PD2 PD3 PD4 SS/ PD5 +V MC68HC11 3K IRQ LFLAG/ MOSI SCK MISO MOSI SCK SS/ LS7366 fCKO 15pF fCKI 1M 40MHz 15pF
FIGURE 12. LS7366 TO MC68H11 SPI PORT INTERFACE
7366-112204-10

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